1. Field of the Invention
The present invention relates to a display driver circuit of a display device. In particular, the present invention relates to a display driver circuit of a display device employing an inversion driving method.
2. Description of Related Art
FIG. 1 is a block diagram schematically showing a configuration of a typical active-matrix liquid crystal display device 1. The liquid crystal display device 1 is provided with a display panel 2 on which an image is displayed. The display panel 2 has a plurality of pixels 3 arranged in a matrix form. Moreover, a plurality of scanning lines X1 to Xm and a plurality of source lines (data lines) Y1 to Yn are so formed as to intersect with each other at a plurality of intersections. The plurality of pixels 3 are arranged at the plurality of intersections, respectively.
Each pixel 3 has a TFT (Thin Film Transistor) 4 and a liquid crystal element 5. A gate terminal of the TFT 4 is connected to one scanning line X, a source terminal or a drain terminal of the TFT4 is connected to one source line Y. One end of the liquid crystal element 5 is connected to the drain terminal or the source terminal of the TFT 4, and the other end thereof is connected to a common electrode to which a predetermined common potential VCOM is applied. A pixel potential is applied to the one end of the liquid crystal element 5 from the source line Y through the TFT 4, and the common potential VCOM is applied to the other end of the liquid crystal element 5. It should be noted that the common potential VCOM is applied to the plurality of pixels 3 in common.
The scanning lines X1 to Xm are connected to a gate driver 6, and the source lines Y1 to Yn are connected to a source driver 7. A power source circuit 8 supplies power to each circuit. Moreover, the power source circuit 8 supplies the above-mentioned common potential VCOM to the display panel 2. A control circuit 9 controls an operation of each circuit. More specifically, the control circuit 9 outputs a scanning line drive timing signal to the gate driver 6 and also outputs a source line drive timing signal and a display data to the source driver 7 The display data (image data) is a digital data.
The gate driver 6 selects and drives the plurality of scanning lines X1 to Xm one by one in turn in accordance with the scanning line drive timing signal. On the other hand, the source driver 7 outputs pixel potentials corresponding to gray-scales of the display data to the respective source lines Y1 to Yn in accordance with the source line drive timing signal. As a result, the pixel potentials corresponding to the gray-scales of the display data are respectively applied to the pixels 3 connected to the selected one scanning line X. The scanning lines X1 to Xm are driven in turn and thereby an image is displayed on the display panel 2.
With regard to the typical liquid crystal display device 1, an “inversion driving method” such as a dot inversion driving method, a line inversion driving method and a frame inversion driving method is known as a technique for reducing flicker and suppressing deterioration of the liquid crystal element 5. According to the inversion driving method, “polarity” of the pixel potential applied to the pixels 3 is inverted every predetermined period, or the “polarity” is inverted between the adjacent pixels 3. For example, pixel potentials of the opposite polarities may be applied to the adjacent source lines Y1 and Y2 shown in FIG. 1 (dot inversion driving). Moreover, the polarity of the pixel potential may be inverted every one line period during which one scanning line X is driven (line inversion driving). Furthermore, the polarity of the pixel potential may be inverted every one frame period during which all the scanning lines X1 to Xm are driven (frame inversion driving). It should be noted that the “polarity” generally means whether the pixel potential is positive or negative as compared with the common potential VCOM of the common electrode.
FIG. 2 shows one example of a correspondence relation between the gray-scale and the pixel potential (gray-scale potential) in a case of 64-gradation representation. In the example shown in FIG. 2, the pixel potentials within a range between a potential VDD (e.g. power source potential) and a potential VSS (e.g. ground potential) are used. In the case of the inversion driving method, two types of pixel potentials, namely, a pixel potential on the positive polarity side and a pixel potential on the negative polarity side are used with respect to one gray-scale. For example, let us consider a case where the common potential VCOM is 0.5 VDD. In this case, potentials from 0.5 VDD to VDD equal to or higher than the common potential VCOM are used as the pixel potential on the positive polarity side. On the other hand, potentials from VSS to 0.5 VDD equal to or lower than the common potential VCOM are used as the pixel potential on the negative polarity side.
FIG. 3 schematically shows a configuration of the source driver 7 used in the liquid crystal display device 1 employing the inversion driving method. In particular, FIG. 3 shows a configuration for the dot inversion driving method, illustrating a configuration related to the two adjacent source lines Y1 and Y2. The source driver 7 shown in FIG. 3 includes: latch circuits 111 and 112, a cross switch 120, level shifters 131 and 132, gray-scale potential generation circuits 141 and 142, a DA converter 151 on the positive polarity side, a DA converter 152 on the negative polarity side, a cross switch 160, and output buffers 171 and 172.
The latch circuit 111 latches a display data DATA1 corresponding to a pixel potential V1 output to the source line Y1. On the other hand, the latch circuit 112 latches a display data DATA2 corresponding to a pixel potential V2 output to the source line Y2. The display data DATA1 is output to one of the level shifters 131 and 132 through the cross switch 120, while the display data DATA2 is output to the other of the level shifters 131 and 132 through the cross switch 120. The level shifters 131 and 132 convert potential levels of the received display data and output them to the DA converters 151 and 152, respectively.
The gray-scale potential generation circuit 141 outputs the gray-scale potentials from 0.5 VDD to VDD on the positive polarity side to the DA converter 151. The DA converter 151 on the positive polarity side converts the received display data to a corresponding one of the gray-scale potentials from 0.5 VDD to VDD. On the other hand, the gray-scale potential generation circuit 142 outputs the gray-scale potentials from VSS to 0.5 VDD on the negative polarity side to the DA converter 152. The DA converter 152 on the negative polarity side converts the received display data to a corresponding one of the gray-scale potentials from VSS to 0.5 VDD.
The gray-scale potentials obtained by the DA converters 151 and 152 are output to the output buffers 171 and 172 through the cross switch 160. Each of the output buffers 171 and 172 includes a voltage follower or the like. The output buffer 171 outputs the received one gray-scale potential as the pixel potential V1 to the source line Y1. On the other hand, the output buffer 172 outputs the received one gray-scale potential as the pixel potential V2 to the source line Y2. In this manner, the pixel potential V1 of the positive polarity (or the negative polarity) is output to the source line Y1 while the pixel potential V2 of the negative polarity (or the positive polarity) is output to the source line Y2. In other words, the pixel potentials of the opposite polarities are output to the adjacent source lines Y1 and Y2, respectively, and thus the dot inversion driving is achieved.
FIG. 4 shows an example of a circuit configuration of the source driver 7 shown in FIG. 3 that employs the inversion driving method (refer to Japanese Patent No. 3206590, for example). For simplicity, let us consider a case where one display data DATA is expressed by a two-bit data [D2, D1]. A bit D1B is the inverted bit of the bit D1, and a bit D2B is the inverted bit of the bit D2. Note that the latch circuits 111 and 112, the cross switch 120 and the level shifters 131 and 132 are not shown in FIG. 4. An output circuit 170 in FIG. 4 corresponds to the cross switch 160 and the output buffers 171 and 172 in FIG. 3.
The gray-scale potential generation circuit 141 has serially connected resistive elements and generates a plurality of gray-scale potentials VP1 to VP4 by resistive voltage division. More specifically, the gray-scale potential generation circuit 141 generates gray-scale potentials VP1, VP2, VP3 and VP4 (VP1>VP2>VP3>VP4) within the positive polarity potential range from 0.5 VDD to VDD, based on the potentials VDD, 0.5 VDD and so on. The plurality of gray-scale potentials VP1 to VP4 are output to the DA converter 151 on the positive polarity side The DA converter 151 consists of PMOS transistors Mp1 to Mp8. The potential VDD is applied to back gates of those PMOS transistors Mp1 to Mp8. The DA converter 151 selects one gray-scale potential VP corresponding to the display data [D2, D1] from the plurality of gray-scale potentials VP1 to VP4, and outputs the selected one gray-scale potential VP to the output circuit 170.
The gray-scale potential VP output from the DA converter 151 on the positive polarity side is within the positive polarity potential range from 0.5 VDD to VDD. Since the potential VDD is applied to the back gates of the PMOS transistors Mp5 to Mp8 in the output stage, a drain-substrate (drain-back gate) voltage is “0.5 VDD” at a maximum. Therefore, an intermediate-voltage MOS transistor having a breakdown voltage of about 0.7 to 0.8 VDD is satisfactory.
Similarly, the gray-scale potential generation circuit 142 has serially connected resistive elements and generates a plurality of gray-scale potentials VN1 to VN4 by resistive voltage division. More specifically, the gray-scale potential generation circuit 142 generates gray-scale potentials VN1, VN2, VN3 and VN4 (VN4>VN3>VN2>VN1) within the negative polarity potential range from VSS to 0.5 VDD, based on the potentials VSS, 0.5 VDD and so on. The plurality of gray-scale potentials VN1 to VN4 are output to the DA converter 152 on the negative polarity side. The DA converter 152 consists of NMOS transistors Mn1 to Mn8. The potential VSS is applied to back gates of those NMOS transistors Mn1 to Mn8. The DA converter 152 selects one gray-scale potential VN corresponding to the display data [D2, D1] from the plurality of gray-scale potentials VN1 to VN4, and outputs the selected one gray-scale potential VN to the output circuit 170.
The gray-scale potential VN output from the DA converter 152 on the negative polarity side is within the negative polarity potential range from VSS to 0.5 VDD. Since the potential VSS is applied to the back gates of the NMOS transistors Mn5 to Mn8 in the output stage, a drain-substrate (drain-back gate) voltage is “0.5 VDD” at a maximum. Therefore, an intermediate-voltage MOS transistor having a breakdown voltage of about 0.7 to 0.8 VSS is satisfactory.
The circuit configuration described above can be applied to the case of the positive polarity potential range and the negative polarity potential range as shown in FIG. 2. In recent years, however, application of the liquid crystal display device becomes more diverse and thus there is a case where the positive polarity potential range and the negative polarity potential range are required to partially overlap with each other. For example, a DA converter on the positive polarity side is required to output the gray-scale potential VP in a potential range from 0.4 VDD to VDD and a DA converter on the negative polarity side is required to output the gray-scale potential VN in a potential range from VSS to 0.6 VDD.
FIG. 5 conceptually shows such potential ranges. The DA converter on the positive polarity side is required to output the gray-scale potential VP within a first potential range RP (from VDD to 0.4 VDD). On the other hand, the DA converter on the negative polarity side is required to output the gray-scale potential VN within a second potential range RN (from 0.6 VDD to VSS). The first potential range RP and the second potential range RN partially overlap with each other. In this case, it is no longer possible to separate between the positive polarity and the negative polarity based on the common potential VCOM. The first potential range RP on the positive polarity side is defined as a potential range handled by the DA converter on the positive polarity side, while the second potential range RN on the negative polarity side is defined as a potential range handled by the DA converter on the negative polarity side.
Now let us consider a case where the potential ranges shown in FIG. 5 are handled by the DA converters 151 and 152 shown in FIG. 4. For example, the gray-scale potential VP4 handled by the PMOS transistors Mp4 and Mp8 in the DA converter 151 on the positive polarity side is the gray-scale potential 0.4 VDD lower than the common potential VCOM (=0.5 VDD). In this case, the PMOS transistor Mp8 may fail to output the desired gray-scale potential 0.4 VDD within a predetermined driving period, due to shortage of a gate-source voltage and a substrate bias effect. Also for example, the gray-scale potential VN4 handled by the NMOS transistors Mn1 and Mn5 in the DA converter 152 on the negative polarity side is the gray-scale potential 0.6 VDD higher than the common potential VCOM (=0.5 VDD). In this case, the NMOS transistor Mn5 may fail to output the desired gray-scale potential 0.6 VDD within a predetermined driving period, due to shortage of a gate-source voltage and the substrate bias effect.
As described above, when it is necessary to handle the potential ranges as shown in FIG. 5, the driving capability may be insufficient and thus satisfactory output characteristics may riot be obtained with the circuit configuration shown in FIG. 4. To avoid this problem, a MOS transistor where the driving capability is insufficient may be replaced by a CMOS transfer gate (refer to Japanese Laid-Open Patent Application JP-H04-204689, for example).
As an example, FIG. 6 shows a configuration of a DA converter 152′ on the negative polarity side which is provided with a CMOS transfer gate. More specifically, the DA converter 152′ is provided with PMOS transistors Mp9 and Mp10 in addition to the configuration of the DA converter 152 shown in FIG. 4. The potential VDD is applied to back gates of the PMOS transistors Mp9 and Mp10. The PMOS transistor Mp9 and the NMOS transistor Mn1 constitute one CMOS transfer gate, and the PMOS transistor Mp10 and the NMOS transistor Mn5 constitute another CMOS transfer gate. These CMOS transfer gates handle the above-described gray-scale potential VN4 higher than the common potential VCOM. It is supposed that sufficient driving capability can be obtained by replacing the DA converter 152 shown in FIG. 4 by the DA converter 152′ shown in FIG. 6.
The inventor of the present application has recognized the following points. In FIG. 6, the gray-scale potential VN output from the DA converter 152′ on the negative polarity side is within a potential range from VSS to 0.6 VDD. Since the potential VDD is applied to the back gate of the PMOS transistor Mp10 in the output stage, the maximum value of a drain-substrate (drain-back gate) voltage applied to the PMOS transistor Mp10 is “VDD−VSS”. Thus, an intermediate-voltage MOS transistor having a breakdown voltage of about 0.7 to 0.8 VSS is not satisfactory for the PMOS transistor Mp10.
It is therefore necessary to use a high-voltage MOS transistor instead of the intermediate-voltage MOS transistor as the PMOS transistor Mp10 constituting the CMOS transfer gate in the output stage. The same applies not only to the DA converter on the negative polarity side but also to the DA converter on the positive polarity side.
As described above, in order to handle the potential ranges as shown in FIG. 5, it is necessary to replace some MOS transistors in a typical DA converter by CMOS transfer gates and further to change a part of the CMOS transfer gates to a high-voltage element. This leads to increase in a layout size of the DA converter as a whole. A rate of the layout size increase becomes higher as the number of gray-scale levels is increased.